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  • MajGenRelativity - Thursday, May 31, 2018 - link

    Glad to see 7nm is on track. I'm interested in seeing what happens afterwards, but for me (consumer and system integrator), all that truly matters is what is shipping right now.
  • axfelix - Thursday, May 31, 2018 - link

    3nm sounds extremely made up. I know everyone already talks a lot about how non-Intel fabs tend to inflate (or deflate, I guess) their process size, but 3nm is just a fiction.
  • deepblue08 - Thursday, May 31, 2018 - link

    Everything sounds made-up until it is done. Although, I'm sure 7nm will serve us well for some time.
  • axfelix - Thursday, May 31, 2018 - link

    I'm pretty sure I've read multiple reports (from both Intel and industry groups) that by Intel's numbering, lower than 5nm is physically impossible. It might be that 3nm by non-Intel fabs is roughly equal to Intel's reckoning of 5nm, in which case fair enough, but that is both a stretch and the absolute end of the line.
  • The Chill Blueberry - Thursday, May 31, 2018 - link

    It's close to impossible on silicon. But if they manage to find a better medium, who knows where it'll stop shrinking..
  • axfelix - Thursday, May 31, 2018 - link

    Yeah, I don't want to sound anti-futurist or anything, I think the transistor report I read made clear that it simply wouldn't be viable from a cost perspective to try to shrink any lower for consumer electronics (the implication being that Quantum Computing can do whatever it wants, but we're not going to be recompiling Windows for Quantum platforms) barring some massive breakthrough, given the impracticality.
  • frenchy_2001 - Thursday, May 31, 2018 - link

    People were also already saying that for sub-1um.
    The crowd chanting "the sky is falling" has been around for a long time.
    Technology goes where the money is. If silicon proves a dead end at nanometer scale, someone will find a different solution.
    It's not the only side step in history.
    Gallium Arsenide is already used for higher frequency (at higher power and leakage) and people are looking into carbon nanotubes.
    There may be a pause in progress, but technology marches on...
  • quorm - Thursday, May 31, 2018 - link

    I believe Axfelix is correct. 5/3nm is basically the end of the line, regardless of substrate. My understanding is that at scales below this, quantum effects make behavior unpredictable, outweighing any potential efficiency benefit, assuming you are able to fab something that size with nanotubes or whatever.
  • Alexvrb - Friday, June 1, 2018 - link

    Self-assembling nano-whatsits.
  • FullmetalTitan - Saturday, June 2, 2018 - link

    Those numbers lost their meaning at about 65nm nodes. 5nm and 3nm will be new transistor designs for most designers. Samsung announced gate all around FETs will be introduced at 5nm for instance. But critical dimensions are still in the 2Xnm range for everyone, naming convention only signifies relative performance improvements meeting the revised moore's law constraint of doubling PERFORMANCE rather than transistor density.

    Additionally, anyone with any plan to produce leading edge nodes beyond 2020 is looking into different materials and radical design changes to continue improving efficiency and scale performance.
  • FullmetalTitan - Saturday, June 2, 2018 - link

    The industry consensus seems to be that 7nm will be a long-lived stable node the way 14nm has been. 5nm will be a stepping stone to 3nm, incorporating loads of new design elements. I expect there will be some pretty gnarly growing pains when everyone begins 5nm testing.
  • AJ_NEWMAN - Thursday, May 31, 2018 - link

    Could this be more about EUV with a NA change of 0.33 -> 0.55 could enable a 2 node shrink?

    https://electroiq.com/euvl-focus/2018/03/12/2018-s...

    AJ
  • FullmetalTitan - Saturday, June 2, 2018 - link

    High NA EUV is years away yet, but it's good news that they demonstrated a pellicle with only 2% attenuation finally, that number had been at 10% for a while (and 250W power source was under the industry expectation by about 50%).
  • zodiacfml - Friday, June 1, 2018 - link

    They should. The crypto market (ASICs, GPUs) alone is large enough to justify the investment. Add AI and gaming markets, it becomes a no brainer.
    As already mentioned, they should decide soon as Samsung and TSMC are aggressive.
  • iwod - Friday, June 1, 2018 - link

    The problem is no one knows how long these will last. AI winter, GPU Crypto etc. Fabs take lots of money and time. ( Although TSMC manage to built one within 6 months )

    I do think it is a they should invest more and attract customer like Qualcomm Broadcom to leading node. If they are not in it for a fight then go back to do secondary node like UMC.
  • FullmetalTitan - Saturday, June 2, 2018 - link

    Building a FAB is easy compared to the next part. Tool in and ramp are like 100x harder and always take longer because of quality verification needs.

    The biggest issue in leading node design is cost of development, especially in relation to troubleshooting and reticle revisions. That is only going to get worse as EUV is introduced to designs, because reticle costs are an order of magnitude more when dealing with an EUV reticle than a KrF/ArF system, and yields for EUV masks from the gold standard mask makers are still much much lower than for a DUV reticle
  • boeush - Friday, June 1, 2018 - link

    "over 17 million gates per square mm" - well, a square mm is 1,000,000 nm x 1,000,000 nm, so that makes for ~5882 square nm per gate, or in other words if a gate is visualized as a square, it would be ~76 nm on each side. Granted, that includes spacing between gates - but is still about 10x the claimed minimum feature size (~7 nm).

    Of course, a logic gate these days is still canonically composed from several transistors. One thing to consider in terms of future tech R&D might be to search for simpler, smaller, alternative nano-scale structures and/or materials that can behave like various logic gates but are not built from transistors... Then we might yet squeeze another factor of 100 or more in performance from greater planar gate density, before we hit the ultimate atomic/molecular/quantum wall and have to start evolving our curcuit designs into the 3rd dimension (with all the attendant manufacturing and cooling challenges...)
  • FullmetalTitan - Saturday, June 2, 2018 - link

    That was poor language choice. They 100% meant transistor density, not logic block density. Dense regions like SRAM are going to be far beyond that number, and there is enough dark silicon that the overall average comes down to that final number.

    The scaling issue for transistors in the FinFET era is that they still need multiple layers to create the proper work function (doped silicon, oxide dielectric, interfacial layer, several gate metal layers, active gate polysilicon, another metal layer, and W plug to connect to MOL interconnects). These films are already controlled at the single-digit nm (and sometimes single-digit A) scale. The move to nanowires, or gate all around, is an attempt to increase effective gate length/size for effective transistor switching control, without making the gate PHYSICALLY larger. Most work in node "shrinks" is just geometry tweaks to make the gate more efficient, stress tweaks to make gates faster/slower, etc.
  • levizx - Friday, June 8, 2018 - link

    That's nonsense.

    1. 7nm is not the claimed Minimum Feature Size, rather process name used to refer to Gate Length up until 28nm.
    2. you essentially calculated MMP x CPP, that was NEVER EVER the feature size. Even before FinFET, it's been 3x ~4x the feature size for years - at 65nm it was ~220nm, at 0.13um it was ~ 0.35um.

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