Marvell Announces NVMe Controller for DRAM-Less PCIe 3.0 x2 SSDs
by Anton Shilov on August 17, 2016 7:30 PM EST
Marvell has announced its new controller for affordable and miniature SSDs, the 88NV1160. The chip can be used to build small form-factor SSDs in M.2 as well as BGA packages. The 88NV1160 supports all modern and upcoming types of NAND flash, LDPC error correction, NVMe protocol and other advantages of modern SSD controllers, but it does not require external DRAM buffers so to reduce BOM costs of upcoming SSDs.
The Marvell 88NV1160 is a quad-channel controller that supports PCIe 3.0 x2 interface, NVMe 1.3 protocol (in addition to AHCI) as well as various types of NAND flash memory, including 15 nm TLC, 3D TLC as well as 3D QLC with ONFI 3.0 interface with up to 400 MT/s transfer rates. The 88NV1160 controller is powered by dual-core ARM Cortex-R5 CPUs along with embedded SRAM with hardware accelerators to optimize IOPS performance. The chip supports Marvell’s third-generation LDPC error correction technology (which the company calls NANDEdge ECC) in a bid to enable high endurance of drives featuring ultra-thin TLC or 3D QLC memory.
| Specifications of Marvell 88NV1160 at Glance | |
| Compute Cores | Two ARM Cortex-R5 |
| Host Interface | PCIe 3.0 x2 |
| Protocol of Host Interface | AHCI, NVMe 1.3 |
| Supported NAND Flash Types | 15 nm TLC 3D TLC 3D QLC |
| Supported NAND Flash Interfaces | Toggle 2.0 and ONFi 3.0, up to 400 MT/s |
| Page Sizes | Unknown |
| Number of NAND Channels | 4 channels with 4 CE per channel (16 targets in total) |
| ECC Technology | LDPC (third-generation LDPC ECC by Marvell) |
| Maximum SSD Capacity | 1024 GB (when using 3D QLC ICs with 512 Gb capacity) |
| Maximum Sequential Read Speed | 1600 MB/s |
| Maximum Sequential Write Speed | Unknown, depends on exact type of memory |
| Power Management | Low power management (L1.2) design |
| Package | 9 × 10 mm TFBGA package |
| Voltages | 3.3V/1.8V/1.2V power supply (according to M.2 specs) |
The 88NV1160 controller is specifically tailored for upcoming affordable SSDs, which is why it does not officially support SLC and 2D MLC NAND. Maximum capacity of a 3D QLC-based SSD featuring the 88NV1160 controller is expected to be around 1 TB, which should be enough for entry-level SSDs (as well as solid-state storage solutions for premium tablets, ultrabooks and other types of computing devices). As for performance, Marvell mentioned 1600 MB/s maximum read speed for such SSDs.
The new chip from Marvell is made using 28 nm process technology and is shipped in 9 × 10 mm TFBGA package, which can be used to build SSDs in BGA (M.2-1620 and smaller) packages as well as drives in M.2-2230/2242 form-factors. The 88NV1160 controller uses 3.3V/1.8V/1.2V power supply, in accordance with the M.2 standards.
The 88NV1160 is not the first controller from Marvell that does not require any external DRAM buffers. The company also offers low-cost 88NV1120 with SATA interface as well as 88NV1140 for PCIe 3.0 x1 SSDs. All of the aforementioned controllers are based on two ARM Cortex-R5 cores, feature Marvell’s third-gen LDPC implementation and support modern types of NAND flash memory (15nm 2D TLC and 3D TLC/QLC). However, the new 88NV1160 is the newest DRAM-less controller from the company, which is designed for rather advanced SSDs with up to 1600 MB/s read speed. Still, the 88NV1160 is clearly a solution for affordable drives because unlike the high-end 88SS1093 (or its less advanced brother, the 88SS1094) it does not support 2D MLC and SLC NAND flash and cannot take advantage of eight NAND channels (which is why it does not need PCIe 3.0 x4).
| Comparison of Modern SSD Controllers from Marvell | ||||||
| 88NV1120 | 88NV1140 | 88NV1160 | 88SS1093 | |||
| Compute Cores | Two ARM Cortex-R5 | Three cores | ||||
| Host Interface | SATA | PCIe 3.0 x1 | PCIe 3.0 x2 | PCIe 3.0 x4 | ||
| Protocol of Host Interface | AHCI | AHCI, NVMe 1.3 | NVMe 1.1 | |||
| Supported NAND Flash Types | 15 nm TLC 3D TLC 3D QLC |
15 nm SLC/MLC/TLC 3D NAND |
||||
| Number of NAND Channels | 2 channels 4 CE per channel (8 targets in total) |
4 channels 4 CE per channel (16 targets in total) |
8 channels 4 CE per channel (32 targets in total) |
|||
| ECC Technology | Marvell's third-gen LDPC-based ECC technology | |||||
| Host Memory Buffer | No | Yes | Yes | - | ||
| Package | 8 × 8 mm TFBGA |
9 × 10 mm TFBGA |
BGA | |||
| Compatibility | M.2/BGA SSDs | M.2/2.5" SSDs | ||||
The developer did not reveal when it expects the first SSDs based on the 88NV1160 controller to hit the market, but it indicated that the chip is available for sampling globally. In addition, the company indicated that it offers turnkey firmware to its customers so to enable faster time to market.
Source: Marvell
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revanchrist - Wednesday, August 17, 2016 - link
QLC could be game changing, Toshiba did show off a prototype 100TB QLC SSD at Flash Memory Summit two weeks ago. But a QLC SSD really shouldn't be anything lesser than 1TB in capacity IMHO, otherwise the performance and endurance will be ugly.ImSpartacus - Wednesday, August 17, 2016 - link
Yeah, I don't think you'd see folks do anything less than a TB or maybe a half TB.Samus - Wednesday, August 17, 2016 - link
Toshiba said they are waiting for 64-layer QLC to come online later this year or early next. I think they are currently at 48-layer. This will get them from 256Gbit to 384Gbit, and when factoring in 4 bits per cell, I suspect the minimum marketable capacity will be 1TB because they will effectively have 512GB per package. Having one NAND die on an SSD is basically making an exotic USB flash drive. Even if the controller is multichannel, the queue depth performance will be terrible.extide - Thursday, August 18, 2016 - link
it would be 512Gb not GB -- thats Gigabit -- so 64GB per die. You would still need 16 of them to make 1TB. (Which is the max of this particular controller)frenchy_2001 - Thursday, August 18, 2016 - link
No, his maths are correct (even if skipping a few steps).He is talking about dies (silicon wafer parts) reaching 512Gb.
Each package stacks up to 8 dies in it, making for 512GB per package, hence his post about requiring multiple packages for parallelism and hence requiring at least 1TB for the whole drive (2 packages).
Ian Cutress - Wednesday, August 17, 2016 - link
The ITRS report suggests that TLC will be mainstream for another 10-15 years. QLC is more aimed at Worm (write once, read many) applications that are more for CDN type applications and cold storage. The question is if the data for QLC can stay stable for a sufficient length of time for cold storage will be a difficult oneBlack_ - Thursday, August 18, 2016 - link
It's not that big of problem. Even if you have to rewrite once 6 months or 12 months. It doesn't matter because those rewrites don't have write amplification.frenchy_2001 - Thursday, August 18, 2016 - link
The ITRS report also sometimes misses the mark and gets blindsided by some developments.NAND industry is looking at ways to increase density and with the step back in XY for 3D NAND, they have been talking about QLC for a while (as cell durability in 3D NAND came back up).
Other forms of storage are developing too, like RRAM, coming hopefully next year after over a year of drumming up by intel (Xpoint).
Flunk - Wednesday, August 17, 2016 - link
It's nice to see new PCI-E controllers that can bring down the price of PCI-E drives. This only means good things for consumers.TeXWiller - Thursday, August 18, 2016 - link
I'm too waiting to put those extra PCIe x1 slots into good use in a couple of older machines. 88NV1140 would fit perfectly in that scenario.